`timescale 1ns / 1ps
module basic_1_sim1;
    reg A,B,C,D,E;
    wire Y;
    basic_1 b1(A,B,C,D,E,Y);
    initial
    begin
        A=0;B=0;C=0;D=0;E=0;
        fork
            repeat (5) #5 A=~A;
            repeat (5) #10 B=~B;
            repeat (5) #15 C=~C;
            repeat (5) #20 D=~D;
            repeat (5) #25 E=~E;
        join
    end
    
endmodule
